FIG. 1 is a block diagram of a prior art data input/output circuit 1 for programming memory cells of a non-volatile memory array (such as a flash memory array), and for reading data indicative of the state of those cells. As shown in FIG. 1, an input/output pad 10 is connected to circuit elements which form a data read path 30 and a data write path 32 to a memory array (not shown). Pad 10 is part of the metallization of the integrated circuit containing the memory array and is connected by means of a wire bond to a data pin of the integrated circuit package. There is one data input/output circuit 1 associated with each data input/output line of the memory, with there typically being eight or sixteen data input/output lines depending upon the memory architecture.
Read path 30 and write path 32 are electrically connected to data line 34, which connects those paths to the memory array by means of decoding multiplexer 16. Decoding multiplexer 16 functions to connect read path 30 and write path 32 to a selected one of the plurality of bit lines of the array, where one of the bit lines is represented by line 19. The selected bit line, which is determined by an address provided to the memory, is connected to the drain of the memory cell being read or programmed.
Write path 32 includes a data latch 12 for storing data input by means of pad 10. Latch 12 is activated or enabled by latch enable signal 13. The latched data is then sent to data input buffer 14, which produces the voltage on line 21 which is applied to the bit line of the cell to be programmed. Input buffer 14 is typically implemented in the form of a tri-statable driver having an output which can be placed in a high impedance mode and effectively disabled during a read operation. The disabling of input buffer 14 is achieved by means of tri-state control line 15. Note that even though control line 15 can be used to disable input buffer 14, buffer 14 remains electrically connected to line 21 in this situation. Thus, any capacitance elements contained in buffer 14 remain electrically connected to line 21 even when buffer 14 is disabled. In some implementations, the functions of latch 12 and input buffer 14 may be combined into a single device.
As noted, input buffer 14 is involved in generating and applying the voltage to the bit line of the target cell which is used for programming that cell. Programming a memory cell typically requires that a relatively precise positive voltage and a relatively large amount of current be delivered to the drain of the cell. Input buffer 14 functions to generate this precise voltage at the required current level. This is typically accomplished by generating a precise voltage and placing this voltage on the gate of an output transistor of input buffer 14. The output transistor is usually an N-channel device which has its source connected to line 21 and is in a source-follower configuration.
In order to precisely control the voltage output by buffer 14 on line 21, it is desirable to maintain the gate-to-source voltage V.sub.gs of the output transistor as close to the threshold voltage V.sub.th as possible. As is well known, for an N-channel MOS device operating in the saturation region, the drain to source current, I.sub.ds, is given by: ##EQU1## where .beta. is the MOS transistor gain factor, and V.sub.th is the threshold voltage of the device. The gain factor .beta. is dependent upon both the fabrication process parameters and the device geometry, with the geometry dependence being given by (W/L), where W is the channel width and L is the channel length of the transistor.
As is evident from the relationship for I.sub.ds, with (V.sub.gs -V.sub.th) small, .beta. must be large in order to produce a large current. This is usually accomplished by making (W/L) large, that is, the device itself is made physically larger. For example, in order to provide the 500 microamp current typically required for programming each memory cell in a flash memory array, a device having a width of approximately 1000 microns is required.
However, an undesirable result of the device having a large value of (W/L) is that the junction capacitance, which is proportional to the transistor width W, is also large. As noted, this large capacitance remains electrically connected to line 21 even when the output of input buffer 14 is switched to the high impedance state by the control signal on line 15. Thus, a result of input buffer 14 being designed to generate the precise voltage and high current needed for the programming function is that a large capacitance is also placed in the data write 32 (programming) path. In addition, because data write path 32 and data read path 30 are electrically connected by virtue of their common connection to data line 34, this capacitance is also electrically connected to the read path.
As previously noted, decoding multiplexer 16 is used to access a desired memory cell in the array for purposes of reading data from or writing data to that cell. Thus; when it is desired to program a particular memory cell, multiplexer 16 is used to access the specified cell and input pad 10, latch 12, and input buffer 14 are used as the data path to program that cell by means of data line 34.
When reading a memory cell of the array, multiplexer 16 is again used to access the bit line connected to the selected memory cell in the array. In the event the cell being read is in an erased state, the cell will typically conduct a current which is converted to a voltage on line 19. Sense amplifier 18 determines the state of the cell, i.e., whether it is programmed or erased (corresponding to a binary value of 0 or 1, respectively). This determination is based on comparing the voltage on lines 19 and 34 to a reference voltage. The outcome of this comparison between the two input voltages is an output which is either high or low, corresponding to a digital value of one or zero. The output of sense amplifier 18 is sent to output buffer 20 which drives the data to output pad 10 where it is accessed by a user.
The minimum time required to perform consecutive read operations is primarily determined by the time it takes for the input voltage indicative of a programmed or erased cell state to stabilize to a value which can be unambiguously compared to the reference voltage input to sense amplifier 18. Thus, the input voltage must either converge to and remain at a value greater than the reference voltage, or converge to and remain at a value less than the reference voltage. This amount of time, dt, is related to the capacitance of the circuit path along which the voltage is set up, which includes lines 19, 34 and 21. As is known, this relationship is given by: EQU dt=C(.DELTA.V/I),
where C is the capacitance of the circuit, .DELTA.V is the magnitude of the voltage swing required to go from the present voltage on line 34 (the reference voltage) to that needed to have the output of sense amplifier 18 switch, and I is the current driven along the circuit. Thus, as the capacitance of the circuit is increased, the time required to stabilize the input to the sense amplifier increases.
As the flash memory cells in the array are primarily subjected to reading operations rather than programming operations, the time required for a read operation is very important in determining the overall performance of the memory. However, as has been described, implementing a circuit capable of providing the desired conditions for an efficient programming operation has the effect of placing a large capacitance in the data read path 30. This results in an increase in the minimum read operation time of the device.
Another factor which increases the read operation time arises because the decoding multiplexer 16 must be capable of coupling the relatively high voltages originating from input buffer 14 in programming operations. Such multiplexers typically include N-channel pass transistors which require gate drive voltages in excess of the programming voltage provided by the input buffer 14. Since the programming voltage is almost always larger than the primary supply voltage, the gate drive voltage must be generated by a special circuit, such as a charge pump circuit, to produce a drive voltage which is greater than the primary supply voltage. This requires a level shifting from the primary supply level to the pumped or higher voltage level. This constraint acts to increase the time delay in the path for decoding multiplexer 16 during read operations. In addition, the transistors of decoding multiplexer 16 have to conduct the relatively large currents used for programming and must be a large geometry device, which further adds to the capacitance present in the read path.
What is desired is a data input/output circuit for use in programming and reading a memory array in which the read operation time is not limited by the capacitance of the elements used to program the array. The present invention addresses this problem by providing a relatively precise programming voltage at the necessary current level without significantly adding to the capacitance of the data read line. In addition, the multiplexer used in read operations does not require a large drive voltage and have the inherent time delay in switching between voltage levels. These and other advantages of the present invention will be apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.